لاجڪ گيٽ

صرف AND، OR، ۽ XOR لاجڪ گيٽس استعمال ڪندي 4-بٽ لُڪ اَهيڊ بائنري ايڊر ڊيزائن لاءِ هڪ لاجڪ سرڪٽ ڊاگرام.

هڪ لاجڪ گيٽ (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.

لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر" (MOSFETs) مان ٺهيل آهن. انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو.

لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي الگورٿم ۽ رياضي جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.

ڪمپائونڊ لاجڪ گيٽس AND-OR-invert ۽ OR-AND-invert اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.

ست بنيادي لاجڪ گيٽس آهن:

1. NOT
2. OR
3. NOR (OR بيان جي نفي)
4. AND
5. NAND (AND بيان جي نفي)
6. XOR (خاص OR)
7. XNOR (خاص OR بيان جي نفي)

تاريخ ۽ ترقي

بائنري نمبر سسٽم کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي بائنري سسٽم کان متاثر هو. ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان رياضي ۽ منطق جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.

سال 1886ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا. شروعاتي برقي ميڪاني ڪمپيوٽر ويڪيوم ٽيوب (ٿرميونڪ والوز) يا ٽرانزسٽر (جنهن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز 5.101 جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي 1924ع ۾ پهرين جديد اليڪٽرانڪ AND گيٽ لاءِ فزڪس ۾ 1954ع جو نوبل انعام مليو. ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين).

سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو. منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.

سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو. 1957ع ۾، فروش ۽ ڊيرڪ PMOS ۽ NMOS پلانر گيٽ تيار ڪرڻ جي قابل هئا. پوء بيل ليبز جي هڪ ٽيم PMOS ۽ NMOS گيٽ سان گڏ ڪم ڪندڙ MOS جو مظاهرو ڪيو. ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.

علامتون

A هڪ هم وقت ساز 4-بٽ مٿي/هيٺ (up/down) ڏهاڪي جي ڪائونٽر علامت (74LS192) ANSI/IEEE Std 91-1984 ۽ IEC اشاعت 60617-12 جي مطابق [پن 11 تي "C3" غائب آهي]

عام استعمال ۾ ابتدائي لاجڪ گيٽ لاءِ علامتن جا ٻه سيٽ آهن. ٻئي ANSI/IEEE Std 91-1984 ۾ بيان ڪيا ويا آهن ۽ ان جو اضافي ANSI/IEEE Std 91a-1991 "مخصوص شڪل" سيٽ، روايتي اسڪيميٽڪ جي بنياد تي، سادي ڊرائنگ لاءِ استعمال ڪيو ويندو آهي ۽ 1950ع ۽ 1960ع جي ڏهاڪي جي گڏيل رياستن جي فوجي معيار MIL-STD-806 مان نڪتل آهي. ان کي ڪڏهن ڪڏهن غير رسمي طور تي، ان جي اصليت کي ظاهر ڪندي، "فوجي" طور بيان ڪيو ويندو آهي. "مستطيل شڪل" سيٽ (ANSI Y32.14 تي ٻڌل) ۽ ٻيا ابتدائي صنعت معيار (جيئن بعد ۾ IEEE ۽ IEC پاران بهتر ڪيل) سڀني قسمن جي گيٽ لاءِ مستطيل خاڪا آهن ۽ ڊوائيسز جي تمام گهڻي وسيع رينج جي نمائندگي جي اجازت ڏيڻ ٿا (روايتي علامتن سان ممڪن کان وڌيڪ). IEC معيار، IEC 60617-12، ٻين معيارن پاران اختيار ڪيو ويو آهي. جهڙوڪ يورپ ۾ EN 60617-12:1999، برطانيه ۾ BS EN 60617-12:1999 ۽ جرمني ۾ DIN EN 60617-12:1998.

IEEE Std 91-1984 ۽ IEC 617-12 جو گڏيل مقصد ڊجيٽل سرڪٽ جي پيچيده منطقي ڪمن کي، اسڪيميٽڪ علامتن سان بيان ڪرڻ جو هڪجهڙائي طريقو مهيا ڪرڻ هو. اها ڪم سادي AND ۽ OR گيٽس کان وڌيڪ پيچيده هئا. اهي وچولي پيماني تي سرڪٽ، جهڙوڪ 4-بٽ ڪائونٽر يا وڏي پيماني تي سرڪٽ جهڙوڪ مائڪرو پروسيسر تائين ٿي سگهن ٿا.

IEC 617-12 ۽ ان جو ٻيهر نمبر ٿيل جانشين IEC 60617-12 واضح طور تي "مخصوص شڪل" علامتون نه ٿا ڏيکارين، پر انهن کان منع به نه ڪين. اها، بهرحال، ANSI/IEEE Std 91 ۽ 91a ۾ هن نوٽ سان ڏيکاريل آهن:

"مخصوص شڪل جي علامت (IEC اشاعت 617، حصو 12 جي مطابق) ترجيح نه آهي، پر ان معيار جي تضاد ۾ نه سمجهيو ويندو آهي."

IEC 60617-12 مطابق نوٽ (سيڪشن 2.1) تي مشتمل آهي؛

"جيتوڻيڪ غير ترجيح ڏني وئي آهي. سرڪاري قومي معيارن پاران تسليم ٿيل ٻين علامتن جو استعمال (يعني علامتن جي جاءِ تي مخصوص شڪلون [بنيادي دروازن جي فهرست]) هن معيار سان تضاد ۾ نه سمجهيو ويندو گهرجي. پيچيده علامتن ٺاهڻ لاءِ انهن ٻين علامتن جو استعمال، مثال طور، ايمبيڊڊ علامتن جي طور تي استعمال، جي حوصلا افزائي ڪئي وئي آهي."

اهو سمجهوتو لاڳاپيل IEEE ۽ IEC ورڪنگ گروپن جي وچ ۾، IEEE ۽ IEC معيارن کي هڪ ٻئي سان باهمي تعميل ۾ هجڻ جي اجازت ڏيڻ لاءِ ٿيو.

1980ع جي ڏهاڪي ۾، اسڪيميٽڪ سرڪٽ بورڊ ۽ ڪسٽم IC ٻنهي کي ڊزائين ڪرڻ جو غالب طريقو هو، جيڪو "گيٽ ايري" (Gate Array) جي نالي سان سڃاتو وڃي ٿو. اڄڪلهه ڪسٽم آئي سي ۽ فيلڊ-پروگراميبل گيٽ ايري عام طور تي هارڊويئر وضاحتي ٻولين (HDL)، جهڙوڪ ويريلاگ يا وي ايڇ ڊي ايل، سان ٺهيل آهن.

Type	Distinctive shape (IEEE Std 91/91a-1991)	Rectangular shape (IEEE Std 91/91a-1991) (IEC 60617-12:1997)	Boolean algebra between A and B	Truth table
Single-input gates
Buffer			${A}$	Input Output A Q 0 0 1 1
NOT (inverter)			${\overline {A}}$ or $\neg A$	Input Output A Q 0 1 1 0
In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a bubble and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the positive logic convention or negative logic convention is being used (high voltage level = 1 or low voltage level = 1, respectively). The wedge is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called Direct Polarity Indication. See IEEE Std 91/91A and IEC 60617-12. Both the bubble and the wedge can be used on distinctive-shape and rectangular-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the bubble is meaningful.
Conjunction and disjunction
AND			$A\cdot B$ or $A\land B$	Input Output A B Q 0 0 0 0 1 0 1 0 0 1 1 1
OR			$A+B$ or $A\lor B$	Input Output A B Q 0 0 0 0 1 1 1 0 1 1 1 1
Alternative denial and joint denial
NAND			${\overline {A\cdot B}}$ or $A\uparrow B$	Input Output A B Q 0 0 1 0 1 1 1 0 1 1 1 0
NOR			${\overline {A+B}}$ or $A\downarrow B$	Input Output A B Q 0 0 1 0 1 0 1 0 0 1 1 0
Exclusive or and biconditional
XOR			$A\oplus B$ or $A\veebar B$	Input Output A B Q 0 0 0 0 1 1 1 0 1 1 1 0
The output of a two input exclusive-OR is true only when the two input values are different, and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol.
XNOR			${\overline {A\oplus B}}$ or ${A\odot B}$	Input Output A B Q 0 0 1 0 1 0 1 0 0 1 1 1
Implication and Nonimplication
IMPLY			${\overline {A}}+B$ or $A\rightarrow B$	Input Output A B Q 0 0 1 0 1 1 1 0 0 1 1 1
NIMPLY			$A\cdot {\overline {B}}$ or $A\nrightarrow B$	Input Output A B Q 0 0 0 0 1 0 1 0 1 1 1 0
IMPLY and NIMPLY are not commutative, meaning that changing the order of the operands may change the result. For instance, $A\rightarrow {\overline {B}}$ is false, but ${\overline {A}}\rightarrow B$ is true; likewise, $A\nrightarrow {\overline {B}}$ is true, but ${\overline {A}}\nrightarrow B$ is false.

ڊي مورگن جي برابر علامتون

By use of De Morgan's laws, an AND function is identical to an OR function with negated inputs and outputs. Likewise, an OR function is identical to an AND function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs.

This leads to an alternative set of symbols for basic gates that use the opposite core symbol (AND or OR) but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated.

A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor.

De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons.

ٽرٿ ٽيبلز

Output comparison of various logic gates:

1-input logic gates

Input	Output
A	Buffer	Inverter
0	0	1
1	1	0

2-input logic gates

Input		Output
A	B	AND	NAND	OR	NOR	XOR	XNOR	IMPLY	NIMPLY
0	0	0	1	0	1	0	1	1	0
0	1	0	1	1	0	1	0	1	0
1	0	0	1	1	0	1	0	0	1
1	1	1	0	1	0	0	1	1	0

يونيورسل لاجڪ گيٽس

وڌيڪ ڏسو: Functional completeness

Charles Sanders Peirce (during 1880–1881) showed that NOR gates alone (or alternatively NAND gates alone) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933. The first published proof was by Henry M. Sheffer in 1913, so the NAND logical operation is sometimes called Sheffer stroke; the logical NOR is sometimes called Peirce's arrow. Consequently, these gates are sometimes called universal logic gates.

Logic gate constructions from only NAND or only NOR

Type	NAND construction	NOR construction
NOT
AND
NAND
OR
NOR
XOR
XNOR
IMPLY
NIMPLY

ڊيٽا اسٽوريج ۽ ترتيب وار منطق

Animation of how an SR NOR gate latch works

Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "latch" circuit. Latching circuitry is used in static random-access memory. More complicated designs that use clock signals and that change only on a rising or falling edge of the clock are called edge-triggered "flip-flops". Formally, a flip-flop is called a bistable circuit, because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a register. When using any of these gate setups the overall system has memory; it is then called a sequential logic system since its output can be influenced by its previous state(s), i.e. by the sequence of input states. In contrast, the output from combinational logic is purely a combination of its present inputs, unaffected by the previous input and output states.

These logic circuits are used in computer memory. They vary in performance, based on factors of speed, complexity, and reliability of storage, and many different types of designs are used based on the application.

صنعتي تياري

پڻ ڏسو: Unconventional computing ۽ Semiconductor device fabrication

اليڪٽرانڪ گيٽ

A functionally complete logic system may be composed of relays, valves (vacuum tubes), or transistors.

Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-gain voltage amplifier, which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate.

The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.

For small-scale logic, designers now use prefabricated logic gates from families of devices such as the TTL 7400 series by Texas Instruments, the CMOS 4000 series by RCA, and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by programmable logic devices, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of programmable logic devices such as FPGAs has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed.

An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered.

The output of one gate can only drive a finite number of inputs to other gates, a number called the "fan-out limit". Also, there is always a delay, called the "propagation delay", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed synchronous circuits. Additional delay can be caused when many inputs are connected to an output, due to the distributed capacitance of all the inputs and wiring and the finite amount of current that each output can provide.

Logic families

اصل مضمون جي لاءِ ڏسو Logic family

There are several logic families with different characteristics (power consumption, speed, cost, size) such as: RDL (resistor–diode logic), RTL (resistor–transistor logic), DTL (diode–transistor logic), TTL (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors.

The simplest family of logic gates uses bipolar transistors, and is called resistor–transistor logic (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early integrated circuits. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in diode–transistor logic (DTL). Transistor–transistor logic (TTL) then supplanted DTL.

CMOS diagram of a NOT gate, also known as an inverter. MOSFETs are the most common way to make logic gates.

As integrated circuits became more complex, bipolar transistors were replaced with smaller field-effect transistors (MOSFETs); see PMOS and NMOS. To reduce power consumption still further, most contemporary chip implementations of digital systems now use CMOS logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation.

Other types of logic gates include, but are not limited to:

Logic family	Abbreviation	Description
Diode logic	DL
Tunnel diode logic	TDL	Exactly the same as diode logic but can perform at a higher speed.
Neon logic	NL	Uses neon bulbs or 3-element neon trigger tubes to perform logic.
Core diode logic	CDL	Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level.
4Layer Device Logic	4LDL	Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required.
Direct-coupled transistor logic	DCTL	Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic.
Metal–oxide–semiconductor logic	MOS	Uses MOSFETs (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes PMOS logic, NMOS logic, complementary MOS (CMOS), and BiCMOS (bipolar CMOS).
Current-mode logic	CML	Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels.
Quantum-dot cellular automata	QCA	Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds.
Ferroelectric FET	FeFET	FeFET transistors can retain their state to speed recovery in case of a power loss.

Three-state logic gates

A three-state buffer can be thought of as a switch. If B is on, the switch is closed. If B is off, the switch is open.

اصل مضمون جي لاءِ ڏسو Three-state logic

A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on buses of the CPU to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a multiplexer, which may be physically distributed over separate devices or plug-in cards.

In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit.

Non-electronic logic gates

Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the Harvard Mark I, were built from relay logic gates, using electro-mechanical relays. Logic gates can be made using pneumatic devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale. Various types of fundamental logic gates have been constructed using molecules (molecular logic gates), which are based on chemical inputs and spectroscopic outputs. Logic gates have been made out of DNA (see DNA nanotechnology) and used to create a computer called MAYA (see MAYA-II). Logic gates can be made from quantum mechanical effects, see quantum logic gate. Photonic logic gates use nonlinear optical effects.

In principle any method that leads to a gate that is functionally complete (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates).

پڻ ڏسو

• ڪمپيوٽنگ
• بولين الجبرا
• ڊجيٽل سرڪٽ
• انٽيگريٽڊ سرڪٽ
• پروسيسر
• ٽرٿ ٽيبل
• And-inverter graph
• Boolean algebra topics
• Boolean function
• Depletion-load NMOS logic
• Electronic symbol
• Espresso heuristic logic minimizer
• Emitter-coupled logic
• Fan-out
• Field-programmable gate array (FPGA)
• Flip-flop (electronics)
• Functional completeness
• Integrated injection logic
• Karnaugh map
• Combinational logic
• List of 4000 series integrated circuits
• List of 7400 series integrated circuits
• Logic family
• Logic level
• Logical graph
• Logic redundancy
• Magnetic logic
• NMOS logic
• Parametron
• Processor design
• Programmable logic controller (PLC)
• Programmable logic device (PLD)
• Propositional calculus
• Race hazard
• Reversible computing
• Superconducting computing
• Unconventional computing

وڌيڪ مطالعي لاء

• Bostock, Geoff (1988). Programmable logic devices: technology and applications. McGraw-Hill. ISBN 978-0-07-006611-3.
• Brown, Stephen D.; Francis, Robert J.; Rose, Jonathan; Vranesic, Zvonko G. (1992). Field Programmable Gate Arrays. Kluwer Academic. ISBN 978-0-7923-9248-4.

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